`timescale 1ns / 1ps

`include "data_width.vh"

module schedule #(parameter
    VERTEX_BRAM_DWIDTH  = `VERTEX_BRAM_DWIDTH,
    VERTEX_PIPE_NUM     = `VERTEX_PIPE_NUM,
    EDGE_PIPE_NUM       = `EDGE_PIPE_NUM,
    TOT_EDGE_MASK_WIDTH = `TOT_EDGE_MASK_WIDTH,
    TOT_ACC_ID_WIDTH    = `TOT_ACC_ID_WIDTH,
    DST_ID_DWIDTH       = `DST_ID_DWIDTH,
    VERTEX_MASK_WIDTH   = `VERTEX_MASK_WIDTH,
    DEGREE_DWIDTH       = `DEGREE_DWIDTH
    ) (
        input                                                   clk,
        input                                                   front_rst,
        input [VERTEX_BRAM_DWIDTH * EDGE_PIPE_NUM - 1 : 0]      front_src_p,
        input [DEGREE_DWIDTH * EDGE_PIPE_NUM - 1 : 0]           front_src_degree,
        input                                                   front_src_p_valid,
        input [TOT_EDGE_MASK_WIDTH - 1 : 0]                     front_tot_src_p_mask,
        input [TOT_ACC_ID_WIDTH - 1 : 0]                        front_tot_acc_id,
        input                                                   front_any_dst_data_valid,
        input [DST_ID_DWIDTH * VERTEX_PIPE_NUM - 1 : 0]         front_dst_id,
        input [VERTEX_MASK_WIDTH * VERTEX_PIPE_NUM - 1 : 0]     front_src_p_mask_r,
        input [VERTEX_PIPE_NUM - 1 : 0]                         front_dst_data_valid,

        output                                                  rst,
        output                                                  buffer_full_edge,
        output                                                  buffer_full_vertex,
        output [VERTEX_BRAM_DWIDTH * EDGE_PIPE_NUM - 1 : 0]     src_p,
        output [DEGREE_DWIDTH * EDGE_PIPE_NUM - 1 : 0]          src_degree,
        output [TOT_EDGE_MASK_WIDTH - 1 : 0]                    src_p_mask,
        output [TOT_ACC_ID_WIDTH - 1 : 0]                       tot_acc_id,
        output                                                  src_p_valid,
        output [VERTEX_PIPE_NUM - 1 : 0]                        data_valid,
        output [DST_ID_DWIDTH * VERTEX_PIPE_NUM - 1 : 0]        dst_id,
        output [VERTEX_MASK_WIDTH * VERTEX_PIPE_NUM - 1 : 0]    src_p_mask_r,
        output [VERTEX_PIPE_NUM - 1 : 0]                        dst_data_valid);

    wire                            read_next_valid;
    wire                            edge_buffer_empty, edge_buffer_full;
    wire                            mask_buffer_empty, mask_buffer_full;
    wire [VERTEX_PIPE_NUM - 1 : 0]  dst_buffer_empty, dst_buffer_full;

    assign buffer_full_edge     = edge_buffer_full;
    assign buffer_full_vertex   = dst_buffer_full[0];

    schedule_para_trans P (
        .clk(clk), .front_rst(front_rst),

        .rst(rst));

    schedule_edge E1 (
        .clk(clk), .rst(front_rst),
        .front_src_p(front_src_p),
        .front_src_degree(front_src_degree),
        .front_src_p_valid(front_src_p_valid),
        .read_next_valid(read_next_valid),

        .buffer_empty(edge_buffer_empty),
        .buffer_full(edge_buffer_full),
        .src_p(src_p),
        .src_degree(src_degree),
        .src_p_valid(src_p_valid));

    schedule_mask M1 (
        .clk(clk), .rst(front_rst),
        .front_tot_src_p_mask(front_tot_src_p_mask), .front_tot_acc_id(front_tot_acc_id),
        .front_any_dst_data_valid(front_any_dst_data_valid), .read_next_valid(read_next_valid),

        .buffer_empty(mask_buffer_empty), .buffer_full(mask_buffer_full),
        .src_p_mask(src_p_mask), .tot_acc_id(tot_acc_id));

    generate
        genvar i;
        for (i = 0; i < VERTEX_PIPE_NUM; i = i + 1) begin : M12_BLOCK_1
            schedule_vertex_single V (
                .clk                        (clk),
                .rst                        (front_rst),
                .front_dst_id               (front_dst_id[(i + 1) * DST_ID_DWIDTH - 1 : i * DST_ID_DWIDTH]),
                .front_src_p_mask_r         (front_src_p_mask_r[(i + 1) * VERTEX_MASK_WIDTH - 1 : i * VERTEX_MASK_WIDTH]),
                .front_dst_data_valid       (front_dst_data_valid[i]),
                .front_any_dst_data_valid   (front_any_dst_data_valid),
                .read_next_valid            (read_next_valid),

                .buffer_empty               (dst_buffer_empty[i]),
                .buffer_full                (dst_buffer_full[i]),
                .data_valid                 (data_valid[i]),
                .dst_id                     (dst_id[(i + 1) * DST_ID_DWIDTH - 1 : i * DST_ID_DWIDTH]),
                .src_p_mask_r               (src_p_mask_r[(i + 1) * VERTEX_MASK_WIDTH - 1 : i * VERTEX_MASK_WIDTH]),
                .dst_data_valid             (dst_data_valid[i]));
        end
    endgenerate

    schedule_control C1 (
        .edge_buffer_empty(edge_buffer_empty), .dst_buffer_empty(dst_buffer_empty[0]),

        .read_next_valid(read_next_valid));

endmodule

module schedule_para_trans (
    input       clk,
    input       front_rst,

    output reg  rst);

    always @ (posedge clk) begin
        rst <= front_rst;
    end

endmodule

module schedule_edge #(parameter
    VERTEX_BRAM_DWIDTH = `VERTEX_BRAM_DWIDTH,
    EDGE_PIPE_NUM = `EDGE_PIPE_NUM,
    DEGREE_DWIDTH = `DEGREE_DWIDTH
    ) (
        input                                               clk,
        input                                               rst,
        input [VERTEX_BRAM_DWIDTH * EDGE_PIPE_NUM - 1 : 0]  front_src_p,
        input [DEGREE_DWIDTH * EDGE_PIPE_NUM - 1 : 0]       front_src_degree,
        input                                               front_src_p_valid,
        input                                               read_next_valid,

        output                                              buffer_empty,
        output                                              buffer_full,
        output [VERTEX_BRAM_DWIDTH * EDGE_PIPE_NUM - 1 : 0] src_p,
        output [DEGREE_DWIDTH * EDGE_PIPE_NUM - 1 : 0]      src_degree,
        output                                              src_p_valid);

    schedule_edge_data_fifo sed (
        .clk(clk), .srst(rst),
        .din(front_src_p), .wr_en(front_src_p_valid), .rd_en(read_next_valid),

        .dout(src_p),
        .valid(src_p_valid),
        .empty(buffer_empty), .prog_full(buffer_full));

    schedule_degree_fifo MD2 (
        .clk(clk), .srst(rst),
        .din(front_src_degree), .wr_en(front_src_p_valid), .rd_en(read_next_valid),

        .dout(src_degree));

endmodule

module schedule_mask #(parameter
    TOT_EDGE_MASK_WIDTH = `TOT_EDGE_MASK_WIDTH, TOT_ACC_ID_WIDTH = `TOT_ACC_ID_WIDTH
    ) (
        input                                   clk,
        input                                   rst,
        input [TOT_EDGE_MASK_WIDTH - 1 : 0]     front_tot_src_p_mask,
        input [TOT_ACC_ID_WIDTH - 1 : 0]        front_tot_acc_id,
        input                                   front_any_dst_data_valid,
        input                                   read_next_valid,

        output                                  buffer_empty,
        output                                  buffer_full,
        output [TOT_EDGE_MASK_WIDTH - 1 : 0]    src_p_mask,
        output [TOT_ACC_ID_WIDTH - 1 : 0]       tot_acc_id);

    tot_edge_mask_fifo TEM1 (
        .clk(clk), .srst(rst),
        .din(front_tot_src_p_mask), .wr_en(front_any_dst_data_valid), .rd_en(read_next_valid),

        .dout(src_p_mask), .empty(buffer_empty), .prog_full(buffer_full));

    tot_acc_id_fifo TAI1 (
        .clk(clk), .srst(rst),
        .din(front_tot_acc_id), .wr_en(front_any_dst_data_valid), .rd_en(read_next_valid),
        
        .dout(tot_acc_id));

endmodule

module schedule_vertex_single #(parameter
    DST_ID_DWIDTH = `DST_ID_DWIDTH, VERTEX_MASK_WIDTH = `VERTEX_MASK_WIDTH
    ) (
        input                               clk,
        input                               rst,
        input [DST_ID_DWIDTH - 1 : 0]       front_dst_id,
        input [VERTEX_MASK_WIDTH - 1 : 0]   front_src_p_mask_r,
        input                               front_dst_data_valid,
        input                               front_any_dst_data_valid,
        input                               read_next_valid,

        output                              buffer_empty,
        output                              buffer_full,
        output                              data_valid,
        output [DST_ID_DWIDTH - 1 : 0]      dst_id,
        output [VERTEX_MASK_WIDTH - 1 : 0]  src_p_mask_r,
        output                              dst_data_valid);

    dst_id_fifo DI1 (
        .clk(clk), .srst(rst),
        .din(front_dst_id), .wr_en(front_any_dst_data_valid), .rd_en(read_next_valid),

        .dout(dst_id), .empty(buffer_empty), .prog_full(buffer_full));

    vertex_mask_fifo VM1 (
        .clk(clk), .srst(rst),
        .din(front_src_p_mask_r), .wr_en(front_any_dst_data_valid), .rd_en(read_next_valid),

        .dout(src_p_mask_r));

    valid_fifo DDV1 (
        .clk(clk), .srst(rst),
        .din(front_dst_data_valid), .wr_en(front_any_dst_data_valid), .rd_en(read_next_valid),

        .dout(dst_data_valid), .valid(data_valid));

endmodule

module schedule_control (
    input edge_buffer_empty,
    input dst_buffer_empty,

    output read_next_valid);

    assign read_next_valid = (!(edge_buffer_empty || dst_buffer_empty));

endmodule